As the electrically re-writable (reloadable) non-volatile memory, an highly-integral NAND-cell type EEPROM has been so far well known, in which a memory cell array is composed of a plurality of series-connected writable/erasable cells, and a select gate is connected between an end of each memory cell column and a source line and further between the other end of the memory cell column and a bit line contact, respectively. FIG. 22(a) is a plane view and FIG. 22(b) is an equivalent circuit diagram both showing only one NAND cell section of the memory cell array of the conventional NAND cell type EEPROM. Further, FIG. 23 is a longitudinal cross-sectional view showing the NAND cell section, taken along the line L-L' in FIG. 22(a); and FIGS. 24(a) and 24(b) are both lateral cross-sectional views taken along the lines M-M' and N-N' shown in FIG. 22(a). Further, FIG. 25 is a plane view showing an arrangement of a plurality of NAND cells in the conventional memory cell array; FIG. 26(a) is a plane view showing a select gate contact region (V) or (VI) both shown in FIG. 25 of the conventional NAND cell type EEPROM; FIG. 26(b) is a cross-sectional view taken along the line O-O' shown in FIG. 26; and FIG. 27 is an enlarged perspective view showing an essential portion shown in FIG. 26(b).
With reference to these drawings, the conventional technique of the EEPROM will be explained hereinbelow. Further, in FIGS. 22(a) and 22(b) and FIG. 23, the reference numeral 19 denotes a diffusion layer; 14.sub.1 to 14.sub.8 denote floating gates; 14.sub.9 and 14.sub.10 denote select gate lines; 16.sub.1 to 16.sub.8 (CG.sub.1 to CG.sub.8) denote control gate lines; 16.sub.9 and 16.sub.10 denote select gate over-adjacent wires (a wire adjacent to the upper side of the select gate lines 14.sub.9 and 14.sub.10, respectively); 18 (DL) denotes a bit line; S.sub.1 and S.sub.2 denote select transistors; and M.sub.1 to M.sub.8 denotes memory cells. Further, in FIG. 23, the reference numeral 11 denotes a semiconductor substrate; 13 denotes a gate oxide film; and 15 and 17 denote interlayer insulating films. Further, in FIG. 24, the reference numeral 12 denotes a field oxide film. Further in these respective drawings. the same reference numerals indicate the same composing elements. In particular, as understood in FIG. 23, the select gate lines 14.sub.9 and 14.sub.10 and the floating gates 14.sub.1 to 14.sub.8 are formed as relatively high resistances through the same process and of the same material. The reason is as follows: in the case where the floating gates are formed of n-type poly silicon, for instance, if the concentration of the n-type dopant (e.g., phosphorus) is high, the reliability of the gate oxide film 13 may deteriorate. Further, the select gate over-adjacent wires 16.sub.9 and 16.sub.10, and the control gates 16.sub.1 to 16.sub.8 are formed through the same process and of the same material as relatively low resistances, as compared with those of the select gate lines 14.sub.9 and 14.sub.10 and the floating gates 14.sub.1 to 14.sub.8.
As described above, as the material of the select gate lines 14.sub.9 and 14.sub.10 (shown in FIG. 23), a wire material of relatively high resistance is used. Consequently, the resistances of the select gate lines 14.sub.9 and 14.sub.10 are high, so that the times required to charge and discharge to and from the select gate lines 14.sub.9 and 14.sub.10 are relatively long. Further, in FIG. 22(b), the gate electrodes for driving the element (select gates) S.sub.1 and S.sub.2 are node (select gate lines) 14.sub.9 and 14.sub.10 (shown in FIG. 23). Accordingly, since the necessary charge/discharge times to and from the select gate lines 14.sub.9 and 14.sub.10 are long, there arises a problem in that the necessary operation time including the charge/discharge to and from the select gate lines is lengthened. To shorten the necessary operation time, conventionally, the method of reducing the effective resistances of the select gate lines in the memory cell array has been so far adopted. To realize this method, the select gate contact regions (V) and (VI) as shown in FIG. 25 are used.
In the conventional method shown in FIG. 26, in the select gate contact regions (V) and (VI) shown in FIG. 25, the node 14.sub.9 or 14.sub.10 is connected to the select gate over-adjacent wire 16.sub.9 or 16.sub.10, respectively through the two wire layers 18a and 18b formed of the material the same as that of the bit line 18. FIG. 26(b) is a cross-sectional view taken along the line O-O' in FIG. 26(a), and FIG. 27 is a perspective view showing the essential portion thereof. When the conventional method as explained with reference to FIGS. 26 and 27 are used, it is possible to connect the select gate over-adjacent wire 16.sub.9 or 16.sub.10 formed of a wiring material lower in resistance than that of the select gate line 14.sub.9 or 14.sub.10 to the select gate line 14.sub.9 or 14.sub.10 in the memory cell, with the result that the effective resistance of the select gate line can be reduced. On the other hand, the select gate contact regions (V) and (VI) shown in FIG. 25 are provided at intervals of the bit lines of several tens to several hundreds in the memory cell array. In other words, the select gate lines are formed at many positions of several tens or several hundreds. In this case, the necessary charge/discharge time to and from the select gate lines 14.sub.9 and 14.sub.10 is mainly determined by the charge/discharge time to and from the wiring portions on the high resistance side, in other words, by the charge/discharge time to and from the select gate line portion sandwiched between the two contacts of the select gate line 14.sub.9 or 14.sub.10 and the select gate over-adjacent wire 16.sub.9 or 16.sub.10. As described above, the select gate line is divided into several to several tens by the contact region with the select gate over-adjacent wire 16. As a result, it is possible to reduce the necessary charge/discharge time down to one-fifth to one-several tenth, as compared with the case where the select gate contact regions (V) and (VI) shown in FIG. 25 are not arranged in the memory cell.
As described above, in the conventional method of reducing the charge/discharge time to and from the above-mentioned select gate 14.sub.9 or 14.sub.10, that is, to reduce the effective resistance of the select gate 14.sub.9 or 14.sub.10, the select gate 14.sub.9 or 14.sub.10 is connected to the select gate over-adjacent wires 16.sub.9 or 16.sub.10 in bypass manner in the select gate contact regions (V) and (VI) shown in FIG. 25, respectively. Further, the resistance of the material of these select gate over-adjacent wires 16.sub.9 and 16.sub.10 is usually determined lower than that of the select gates 14.sub.9 and 14.sub.10, so that it is possible to reduce the effective resistance of the select gates 14.sub.9 and 14.sub.10 by connecting the select gate over-adjacent wires 16.sub.9 and 16.sub.10 to the select gates 14.sub.9 and 14.sub.10, respectively.
In the conventional method as described above, however, since the number of the contacts with the wires in the select gate contact regions (V) and (VI) is as large as three per select gate line (as understood in FIG. 27), the width of the select gate contact region must be widened. However, these gate contact regions exist at many positions of several tens in the memory cell array, the area of select gate contact regions increases with increasing width of one select gate region, so that there exists a problem in that the chip area increases markedly. Further, when the number of the select gate contact regions is decreased in the memory cell array, there arises another problem in that the charge/discharge time to and from the select gate increases, with the result that the necessary operation time including the select gate line charge/discharge operation time is lengthened.
On the other hand, FIG. 28 shows another conventional example in which two adjacent select gate lines (e.g., SG.sub.1 and SG.sub.2 of FIG. 25), only if both select gate lines are controled and driven in common, are formed integral with each other to bypass the select gate lines through a single bit line 18 simultaneously. However, since the cross-section of this example can be also shown in FIG. 26(b), the problems involved in this conventional example is the same as with the conventional case already explained.
Further, FIGS. 29(a) to 29(c) show still another example of the conventional method, in which the bit line 18 is formed by a wiring layer formed on the select gate lines 14 and 16 and further the bit line contact opening is tapered to increase the processing margin. In this method, as shown in FIG. 29(a), the contact hole is etched by anisotropic etching (RIE) and further by isotropic etching by leaving the resist R.sub.10 to form the upper contact hole C.sub.10. Since the upper contact hole C.sub.10 can be formed, it is possible to prevent the wiring layer 18 from being cut off at the contact portion. In this method, however, when the isotropic etching rate is large, there exists a possibility that the wire 16 is shorted to the bit line 18. After that, as understood by FIG. 29(b), the lower contact hole C.sub.11 is formed by the isotropic etching. After that, the resist R.sub.10 has been removed, the bit line is buried in the formed hole.
As described above, in the conventional NAND type EEPROM, the width of the select gate contact regions must be determined wide. However, since these select contact gate regions exist at as many positions as several tens in the memory cell array, there exists a problem in that the chip area inevitably increases. In addition, when the number of the select gate contact regions is reduced in the memory cell array for prevention of an increase of the chip area, there arises the other problem in that the time required for charge/discharge to and from the select gage lines is lengthened and thereby the necessary operation time including the charge/discharge time to and from the select gate line is lengthened.